1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit system, and particularly, to a high-speed clock-synchronous semiconductor integrated circuit.
2. Description of the Related Art
The operating frequencies of CPUs (central processing units) or the frequencies of clock signals to drive CPUs are increasing rapidly, and therefore, memories such as DRAMs (dynamic random access memories) connected to the CPUs must operate at high speed.
There have been proposed high-speed DRAMs such as DDR (double data rate) DRAMs that are accessible in response to not only rises of a clock signal but also falls thereof.
When access intervals and clock frequencies for a system having a CPU and a memory are made faster, the difference in wiring load between a data bus and a clock line between the CPU and the memory causes a skew of signals transmitted through the data bus with respect to a clock signal transmitted through the clock line. It is necessary to provide a semiconductor integrated circuit that is capable of reducing such a skew of signals.
The related art high-speed clock-synchronous semiconductor integrated circuit and problems associated with the related art semiconductor integrated circuit will be described in detail later with reference to the drawings.